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cpu: add LLACQ_SCREL, SCQ, DBAR_HINTS detection for loong64

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These three feature detections have been implemented in the Go mainline.

Change-Id: I9c264f7dac0630931d851c04f904d4365d70a28b
Reviewed-on: https://go-review.googlesource.com/c/sys/+/779781
LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Meidan Li <limeidan@loongson.cn>
Reviewed-by: David Chase <drchase@google.com>
Reviewed-by: Michael Pratt <mpratt@google.com>
Auto-Submit: abner chenc <chenguoqi@loongson.cn>
This commit is contained in:
Guoqi Chen
2026-05-20 06:06:04 -07:00
committed by Gopher Robot
parent 99666ae32e
commit 758f71cb83
2 changed files with 25 additions and 9 deletions
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cpu/cpu.go
+11 -7
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@@ -152,13 +152,17 @@ var ARM struct {
// The booleans in Loong64 contain the correspondingly named cpu feature bit.
// The struct is padded to avoid false sharing.
var Loong64 struct {
_ CacheLinePad
HasLSX bool // support 128-bit vector extension
HasLASX bool // support 256-bit vector extension
HasCRC32 bool // support CRC instruction
HasLAM_BH bool // support AM{SWAP/ADD}[_DB].{B/H} instruction
HasLAMCAS bool // support AMCAS[_DB].{B/H/W/D} instruction
_ CacheLinePad
_ CacheLinePad
HasLSX bool // support 128-bit vector extension
HasLASX bool // support 256-bit vector extension
HasCRC32 bool // support CRC instruction
HasLAMCAS bool // support AMCAS[_DB].{B/H/W/D}
HasLAM_BH bool // support AM{SWAP/ADD}[_DB].{B/H} instruction
HasLLACQ_SCREL bool // support LLACQ.{W/D}, SCREL.{W/D} instruction
HasSCQ bool // support SC.Q instruction
HasDBAR_HINTS bool // supports finer-grained DBAR hints
_ CacheLinePad
}
// MIPS64X contains the supported CPU features of the current mips64/mips64le