From 758f71cb839d131daf0ba4befa6a2c6ceb21a649 Mon Sep 17 00:00:00 2001 From: Guoqi Chen Date: Wed, 20 May 2026 14:25:58 +0800 Subject: [PATCH] cpu: add LLACQ_SCREL, SCQ, DBAR_HINTS detection for loong64 These three feature detections have been implemented in the Go mainline. Change-Id: I9c264f7dac0630931d851c04f904d4365d70a28b Reviewed-on: https://go-review.googlesource.com/c/sys/+/779781 LUCI-TryBot-Result: golang-scoped@luci-project-accounts.iam.gserviceaccount.com Reviewed-by: Meidan Li Reviewed-by: David Chase Reviewed-by: Michael Pratt Auto-Submit: abner chenc --- cpu/cpu.go | 18 +++++++++++------- cpu/cpu_loong64.go | 16 ++++++++++++++-- 2 files changed, 25 insertions(+), 9 deletions(-) diff --git a/cpu/cpu.go b/cpu/cpu.go index 63541994..ccdd0610 100644 --- a/cpu/cpu.go +++ b/cpu/cpu.go @@ -152,13 +152,17 @@ var ARM struct { // The booleans in Loong64 contain the correspondingly named cpu feature bit. // The struct is padded to avoid false sharing. var Loong64 struct { - _ CacheLinePad - HasLSX bool // support 128-bit vector extension - HasLASX bool // support 256-bit vector extension - HasCRC32 bool // support CRC instruction - HasLAM_BH bool // support AM{SWAP/ADD}[_DB].{B/H} instruction - HasLAMCAS bool // support AMCAS[_DB].{B/H/W/D} instruction - _ CacheLinePad + _ CacheLinePad + HasLSX bool // support 128-bit vector extension + HasLASX bool // support 256-bit vector extension + HasCRC32 bool // support CRC instruction + HasLAMCAS bool // support AMCAS[_DB].{B/H/W/D} + HasLAM_BH bool // support AM{SWAP/ADD}[_DB].{B/H} instruction + HasLLACQ_SCREL bool // support LLACQ.{W/D}, SCREL.{W/D} instruction + HasSCQ bool // support SC.Q instruction + HasDBAR_HINTS bool // supports finer-grained DBAR hints + + _ CacheLinePad } // MIPS64X contains the supported CPU features of the current mips64/mips64le diff --git a/cpu/cpu_loong64.go b/cpu/cpu_loong64.go index 45ecb29a..8c234b44 100644 --- a/cpu/cpu_loong64.go +++ b/cpu/cpu_loong64.go @@ -15,8 +15,13 @@ const ( cpucfg1_CRC32 = 1 << 25 // CPUCFG2 bits - cpucfg2_LAM_BH = 1 << 27 - cpucfg2_LAMCAS = 1 << 28 + cpucfg2_LAM_BH = 1 << 27 + cpucfg2_LAMCAS = 1 << 28 + cpucfg2_LLACQ_SCREL = 1 << 29 + cpucfg2_SCQ = 1 << 30 + + // CPUCFG3 bits + cpucfg3_DBAR_HINTS = 1 << 17 ) func initOptions() { @@ -26,6 +31,9 @@ func initOptions() { {Name: "crc32", Feature: &Loong64.HasCRC32}, {Name: "lam_bh", Feature: &Loong64.HasLAM_BH}, {Name: "lamcas", Feature: &Loong64.HasLAMCAS}, + {Name: "llacq_screl", Feature: &Loong64.HasLLACQ_SCREL}, + {Name: "scq", Feature: &Loong64.HasSCQ}, + {Name: "dbar_hints", Feature: &Loong64.HasDBAR_HINTS}, } // The CPUCFG data on Loong64 only reflects the hardware capabilities, @@ -37,10 +45,14 @@ func initOptions() { // through CPUCFG cfg1 := get_cpucfg(1) cfg2 := get_cpucfg(2) + cfg3 := get_cpucfg(3) Loong64.HasCRC32 = cfgIsSet(cfg1, cpucfg1_CRC32) Loong64.HasLAMCAS = cfgIsSet(cfg2, cpucfg2_LAMCAS) Loong64.HasLAM_BH = cfgIsSet(cfg2, cpucfg2_LAM_BH) + Loong64.HasLLACQ_SCREL = cfgIsSet(cfg2, cpucfg2_LLACQ_SCREL) + Loong64.HasSCQ = cfgIsSet(cfg2, cpucfg2_SCQ) + Loong64.HasDBAR_HINTS = cfgIsSet(cfg3, cpucfg3_DBAR_HINTS) } func get_cpucfg(reg uint32) uint32