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cpu: add HPDS, LOR, PAN detection for arm64

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This CL gets ID_AA64MMFR1_EL1, Memory Model Feature Register 1, and
grabs HPDS, LOR, PAN features from its bits.

Fixes golang/go#75472.

Change-Id: Ic04b109d79aceba9b3b1d3a1ea514fcf132007c5
GitHub-Last-Rev: f938ff468bca49cc7863aa26e7a880eec2823bb4
GitHub-Pull-Request: golang/sys#263
Reviewed-on: https://go-review.googlesource.com/c/sys/+/704075
Reviewed-by: Keith Randall <khr@google.com>
Auto-Submit: Keith Randall <khr@golang.org>
Reviewed-by: Michael Knyszek <mknyszek@google.com>
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Keith Randall <khr@golang.org>
This commit is contained in:
Chongyi Zheng
2025-10-28 09:43:50 -07:00
committed by Gopher Robot
parent ea436ef09d
commit 6239615695
7 changed files with 33 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
cpu/cpu_arm64.go
+18 -2
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@@ -65,10 +65,10 @@ func setMinimalFeatures() {
func readARM64Registers() {
Initialized = true
parseARM64SystemRegisters(getisar0(), getisar1(), getpfr0())
parseARM64SystemRegisters(getisar0(), getisar1(), getmmfr1(), getpfr0())
}
func parseARM64SystemRegisters(isar0, isar1, pfr0 uint64) {
func parseARM64SystemRegisters(isar0, isar1, mmfr1, pfr0 uint64) {
// ID_AA64ISAR0_EL1
switch extractBits(isar0, 4, 7) {
case 1:
@@ -152,6 +152,22 @@ func parseARM64SystemRegisters(isar0, isar1, pfr0 uint64) {
ARM64.HasI8MM = true
}
// ID_AA64MMFR1_EL1
switch extractBits(mmfr1, 12, 15) {
case 1, 2:
ARM64.HasHPDS = true
}
switch extractBits(mmfr1, 16, 19) {
case 1:
ARM64.HasLOR = true
}
switch extractBits(mmfr1, 20, 23) {
case 1, 2, 3:
ARM64.HasPAN = true
}
// ID_AA64PFR0_EL1
switch extractBits(pfr0, 16, 19) {
case 0: