cpu: use MRS instruction to read arm64 system registers

Use the MRS instruction with the corresponding system register instead
of encoding the instructions using a WORD directive.

Change-Id: I2995dfa6ad731cb03867160127db84898adfdda5
Reviewed-on: https://go-review.googlesource.com/c/sys/+/583135
LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
Reviewed-by: Michael Knyszek <mknyszek@google.com>
Reviewed-by: David Chase <drchase@google.com>
Auto-Submit: Tobias Klauser <tobias.klauser@gmail.com>
This commit is contained in:
Tobias Klauser
2025-10-31 12:39:58 -07:00
committed by Gopher Robot
parent 2a15272850
commit 3675c4cc48
+4 -8
View File
@@ -9,16 +9,14 @@
// func getisar0() uint64 // func getisar0() uint64
TEXT ·getisar0(SB),NOSPLIT,$0-8 TEXT ·getisar0(SB),NOSPLIT,$0-8
// get Instruction Set Attributes 0 into x0 // get Instruction Set Attributes 0 into x0
// mrs x0, ID_AA64ISAR0_EL1 = d5380600 MRS ID_AA64ISAR0_EL1, R0
WORD $0xd5380600
MOVD R0, ret+0(FP) MOVD R0, ret+0(FP)
RET RET
// func getisar1() uint64 // func getisar1() uint64
TEXT ·getisar1(SB),NOSPLIT,$0-8 TEXT ·getisar1(SB),NOSPLIT,$0-8
// get Instruction Set Attributes 1 into x0 // get Instruction Set Attributes 1 into x0
// mrs x0, ID_AA64ISAR1_EL1 = d5380620 MRS ID_AA64ISAR1_EL1, R0
WORD $0xd5380620
MOVD R0, ret+0(FP) MOVD R0, ret+0(FP)
RET RET
@@ -33,15 +31,13 @@ TEXT ·getmmfr1(SB),NOSPLIT,$0-8
// func getpfr0() uint64 // func getpfr0() uint64
TEXT ·getpfr0(SB),NOSPLIT,$0-8 TEXT ·getpfr0(SB),NOSPLIT,$0-8
// get Processor Feature Register 0 into x0 // get Processor Feature Register 0 into x0
// mrs x0, ID_AA64PFR0_EL1 = d5380400 MRS ID_AA64PFR0_EL1, R0
WORD $0xd5380400
MOVD R0, ret+0(FP) MOVD R0, ret+0(FP)
RET RET
// func getzfr0() uint64 // func getzfr0() uint64
TEXT ·getzfr0(SB),NOSPLIT,$0-8 TEXT ·getzfr0(SB),NOSPLIT,$0-8
// get SVE Feature Register 0 into x0 // get SVE Feature Register 0 into x0
// mrs x0, ID_AA64ZFR0_EL1 = d5380480 MRS ID_AA64ZFR0_EL1, R0
WORD $0xd5380480
MOVD R0, ret+0(FP) MOVD R0, ret+0(FP)
RET RET